Welcome to the uEAC Project
This project is dedicated to the design and development of the Extended Analog Computer. The Extended Analog Computer is a new paradigm in computation that provides a flexible physical framework for evolutionary algorithms use in developing solutions.
sEACer
sEACer is a simulator for multi-sheet eac architectures. The simulator allows the temporal properties of both the sheet and the Lukasiewicz logic arrays. The simulator has been designed to allow multiple digital servers to be utilized to execute the simulation.
uEAC R002
The uEAC R002 board is a physical embodiment of the Extended Analog Computer. It is uses a 5x5 matrix of analog cells as a fabric for evolutionary algorithm development.
uEAC System Overview Presentation - covers the basics of the hardware and the simulator
Photo Gallery of the uEAC R002 hardware
uEAC Simulator: Be sure to checkout the Overview Presentation above for operation details !
Maintained by Bryce Himebaugh (bhimebau@…)
