Homework

The following is for Spring 2009

• Homework 1, Due 1/20. From Winkel Chapter 1
  • 1-4
  • 1-8 a d g
  • 1-9
  • 1-12
  • 1-14
  • 1-15
  • 1-16
  • 1-35a display Hexadecimal A-F as A b C d E F (as nearly as you can)
• Homework 2, Due 1/27. From Winkel Chapters 2 and 3
  • 2-15 -- simulate using Quartus II. Turn in simulation output. Caution, make sure you change signal values slowly (e.g. every 50ns) otherwise you'll be confused by the output.
  • 2-21
  • 3-9
  • 3-13
• Homework 2 Makeup (From Winkel 2,3)
  • 2-20
  • 3-16
  • 3-19
• Homework 3, Due 2/5 -- implement a 16-bit carry lookahead adder (4-bit carry units)

in VHDL. Your design should consist of two verilog modules -- the carry unit and the adder -- tied together in a schematic. The inputs to the schematic should be A[15..0], B[15..0], and cin. The outputs should be S[15.00] and cout. Simulate your design for a handful of "corner cases". Turn in the vhdl files, your schematic, and the waveform from simulation.

• Homework 3 makeup. The same except make a borrow lookahead subtractor. P and G

must be redefined appropriately to generate borrow in place of carry.

• Homework 4, Due 2/10
  • Read chapters 3,4 of vhdl book
  • problem 3.2 from Pedroni
  • problems 4.1, 4.3 from Pedroni
• Homework 4 makeup
  • Problems 3.1, 3.5 from Pedroni
  • Problem 4.4 from Pedroni
• Homework 5, Due 3/26
  • problems 8.1,8.2 from Pedroni

These are from last year --- For reference only !

• Homework 2, Due 1/24. From Winkel Chapter 3. For questions requiring simulation, use Quartus and turn in the resulting simulation output.
  • 3.7
  • 3.13
  • 3.14 (a is strictly optional)
  • 3.15
• Read the following verilog tutorials
  • Quartus II Introduction for Verilog Users
  • Introduction to Verilog
• Homework 3 Due 2/7
  • Design a master/slave D-latch using primitive gates in verilog (http://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#D_flip-flop) and simulate using quartus. Turn in your verilog and the simulator output demonstrating correct behavior.
  • Implement figure 4-18 in verilog by writing a tff module and then the four bit counter
  • Implement figure 4-23 in verilog by defining a 1-bit cell and using this to build a 4-bit version
  • Implement figure 4-23 in verilog using a purely behavioral approach (i.e. multibit operators.
• Homework 4, Due 2/14. A common performance enhancement strategy trades latency for

throughput by utilizing pipelining. In a pipelined architecture, an operation may take multiple clock periods to complete, but a new operation may be launched every cycle. To demonstrate this principle, implement the 12 bit pipelined architecture illustrated in http://cis.stanford.edu/icl/wooley-grp/katayoun/orals_katy_hard/sld024.htm. The "latches" are clocked storage (e.g. d flip-flops). You should implement this as a collection of verilog modules tied together as a schematic in the form of the linked figure. You should develop a simulation waveform illustrating the addition of streams of 12 bit values -- one every clock period.